Semiconductor fabrication processes often involve deposition of metals into features, such as vias or trenches, to form contacts or interconnects. However, as devices shrink, features become smaller and harder to fill, particularly in advanced logic and memory applications. New fill materials and techniques have been proposed. Current technology for preparing a feature on a semiconductor substrate to be filled with some of these materials/techniques is a wet clean. A problem with wet clean is that it is not generally selective for etching in the field around the feature opening or neck area of the feature opening alone, as would be desirable. A general wet etching/clean chemistry also removes deposited metal or catalytic deposition seed film from the bottom of the feature structure resulting in failure of bottom-up fill. And partial or incomplete removal of metal or a catalytic layer from the field and neck can result in early pinch-off and void formation.